1. Field of the Invention
The present invention relates to slurry compositions and methods using such slurry compositions for the chemical mechanical polishing (CMP) of material layers deposited during the manufacture of semiconductor devices, more particularly to slurry compositions including one or more additives for adjusting the relative removal rates of different materials, and most particularly to slurry compositions including one or more additives for reducing the removal rate of polysilicon relative to other materials present on a semiconductor substrate.
2. Description of the Related Art
The increasing demand for high performance semiconductor devices and the corresponding demand for increased degrees of integration for modern semiconductor devices require the use of fine pitch multilayer interconnection structures. These multilayer interconnection structures are typically formed by processes that involve sequential insulator deposition, patterning, etching, conductor deposition and planarization steps. The planarization steps are particularly important for providing a substantially planar surface for subsequent deposition and patterning processes that can consistently produce patterns having critical dimensions falling within narrow sizing ranges.
A variety of planarization methods have been utilized depending on the particular semiconductor fabrication process and the specific patterns and material layers being used at a particular step within the fabrication process. Planarization techniques have included forming a layer or a coating of an insulator, such as silicon dioxide, a conductor, such as copper, a resin, such as polyimide, a spin-on-glass (SOG), or a doped glass, such as borophosphosilicate glass (BPSG), followed by one or more processes such as etch-back, reflow, and/or CMP steps to obtain a more planar surface for subsequent processing.
In CMP processes, the semiconductor substrate is typically mounted on a rotating plate or other holder, and the surface of the substrate is then brought into contact with a polishing surface of a polishing pad. Portions of the material layers and/or patterns formed on the substrate are then removed by causing relative motion between the substrate and the polishing pad while providing a supply of one or more slurry compositions to the polishing surface of the polishing pad. Depending on the materials being removed, a CMP process may be primarily mechanical, wherein the material is removed by an abrasive, or a combination of chemical action between one or more components of the slurry and the one or more of the materials being removed and the mechanical action of the polisher.
During the planarizing process, the polishing surface of the polishing pad will typically be continuously wetted with an abrasive slurry and/or a planarizing liquid to produce the desired planarizing surface. The substrate and/or the planarizing surface of the pad are then urged into contact to establish a planarizing load or pressure and moved relative to one another to cause the planarizing surface to begin removing an upper portion of the material layer. The relative motion of the substrate and the polishing surface can be simple or complex and may include one or more lateral, rotational, revolving or orbital movements by the planarizing pad and/or the substrate in order to produce generally uniform removal of the material layer across the surface of the substrate.
As used herein, lateral movement is movement in a single direction, rotational movement is rotation about an axis through the center point of the rotating object, revolving movement is rotation of the revolving object about a non-centered axis and orbital movement is rotational or revolving movement combined with an oscillation. Although, as noted above, the relative motion of the substrate and the planarizing pad may incorporate different types of movement, the motion must typically be confined to a plane substantially parallel to the surface of substrate in order to achieve a planarized substrate surface.
The particular slurry composition, as well as the parameters under which the CMP are conducted will typically be a function of the particular characteristics of the various primary and secondary materials to be removed from the substrate surface. In particular, in a case where a polysilicon layer and a silicon oxide layer are being polished using a silica-based slurry using silica (SiO2) as primary abrasive, the removal rate of the polysilicon will tend to be higher than the removal rate of the silicon oxide. These differing removal rates for different materials under substantially identical polishing conditions are typically expressed as a selectivity ratio. CMP processes are commonly arranged to take advantage of these differences in removal rate by providing a polishing stopping layer, e.g., a material with a much lower removal rate, below the primary layer of material being removed to allow sufficient overpolishing to account for variations in layer thicknesses and wafer planarity. This overpolishing increases the likelihood that substantially all of the intended material layer can be removed without damaging the underlying patterns. In certain instances, however, it may not be possible or practical to utilize a polishing stopping layer, or the relative characteristics of the materials being removed can tend to result in “dishing” or “cupping” of the more easily removed material and produces a more non-planar surface than desired and may compromise subsequent processing.
For example, as illustrated in FIGS. 1A-D, the removal of the upper portion of a polysilicon layer deposited over a silicon nitride pattern can result in a substantially non-planar surface. As illustrated in FIG. 1A, a substrate 100 has an active region 102 separated by isolation regions 104. The active region 102, will also typically include one or more doped regions (not shown) to which electrical contact must be made in order for the final semiconductor device to operate properly. A pattern of gate electrodes 106 or other structures are then formed on the substrate. The gate electrodes 106, which may have a stacked structure including polysilicon 108 and a metal silicide 110, formed by reacting a metal, such as tungsten, cobalt or nickel, or a metal alloy with a portion of the polysilicon, are protected by an insulating spacer structure 112, typically including silicon dioxide and/or silicon nitride. Between the spacer structures 112, contact portions of the surface of the semiconductor substrate will be exposed and a polysilicon layer 114 will be deposited on the structure as a means of establishing electrical contact to the substrate.
As illustrated in FIG. 1B, the upper portion of the polysilicon layer 114 is then removed to form polysilicon plugs 114a between the spacer structures 112. However, because polysilicon may be removed at a rate greater than the rate at which silicon oxide or silicon nitride are removed, in some instances as much as 50 to 100 times greater, there is a tendency for excessive polysilicon to be removed, forming depressions 116 between the spacer structures and produce a non-planar surface. As illustrated in FIG. 1C, once the CMP process has been completed, an interlayer dielectric layer (ILD) 118, may be deposited on the substrate. A photoresist contact pattern (not shown) will then be formed on the ILD 118 and the ILD material etched to form contact openings 120 that extend through the ILD to expose a surface of the polysilicon pads or plugs 114a. 
However, as a result of the excessive polysilicon removal, the surface of the polysilicon plugs 114a is recessed relative to the upper surfaces of the spacer structures 112, increasing the thickness of the ILD 118 that must be removed to open the contacts. This increased thickness can result in problems such as the underetch condition illustrated in FIG. 1E wherein the etch is not sufficient to open some or all of the contact openings, leaving regions of residual ILD 118a in the bottom of the contact openings. Similarly, as illustrated in FIG. 1F, in those instances in which the depth of the etch is sufficient to reach the polysilicon, but the contact pattern is misaligned, the contacts openings can expose the gate electrodes 106 or other conductive structures, causing shorts in region S. Both opens and shorts will reduce the process yield and/or reduce the reliability of the final semiconductor devices.